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CY7C107D CY7C1007D
1-Mbit (1M x 1) Static RAM
Features
* Pin- and function-compatible with CY7C107B/CY7C1007B * High speed -- tAA = 10 ns * Low Active Power -- ICC = 80 mA @ 10 ns * Low CMOS Standby Power -- ISB2 = 3 mA * 2.0V Data Retention * Automatic power-down when deselected * CMOS for optimum speed/power * TTL-compatible inputs and outputs * CY7C107D available in Pb-free 28-pin 400-Mil wide Molded SOJ package. CY7C1007D available in Pb-free 28-pin 300-Mil wide Molded SOJ package
Functional Description [1]
The CY7C107D and CY7C1007D are high-performance CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and tri-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when deselected. The output pin (DOUT) is placed in a high-impedance state when: * Deselected (CE HIGH) * When the write operation is active (CE and WE LOW) Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A19). Read from the device by taking Chip Enable (CE) LOW while while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the data output (DOUT) pin.
Logic Block Diagram
DIN A0 A1 A2 A3 A4 A5 A6 A7 A8 CE WE
INPUT BUFFER
ROW DECODER
1M x 1 ARRAY
SENSE AMPS
DOUT
COLUMN DECODER
POWER DOWN
Note 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05469 Rev. *G
*
198 Champion Court
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
*
San Jose, CA 95134-1709 * 408-943-2600 Revised December 8, 2010
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CY7C107D CY7C1007D
Pin Configuration [2]
SOJ Top View
A10 A11 A12 A13 A14 A15 NC A16 A17 A18 A19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A9 A8 A7 A6 A5 A4 NC A3 A2 A1 A0 DIN CE
DOUT WE GND
Selection Guide
CY7C107D-10 CY7C1007D-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current, ISB2 10 80 3 Unit ns mA mA
Note 2. NC pins are not connected on the die.
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CY7C107D CY7C1007D
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature 65C to +150C Ambient Temperature with Power Applied 55C to +125C Supply Voltage on VCC Relative to GND [3] 0.5V to +6.0V DC Voltage Applied to Outputs in High-Z State [3] 0.5V to VCC + 0.5V DC Input Voltage [3] 0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 5V 0.5V Speed 10 ns
Electrical Characteristics (Over the Operating Range)
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage
[3]
Test Conditions IOH = 4.0 mA IOL = 8.0 mA
7C107D-10 7C1007D-10 Min 2.4 0.4 2.2 0.5 VCC + 0.5 0.8 +1 +1 80 72 58 37 10 3 Max
Unit V V V V A A mA mA mA mA mA mA
Input Leakage Current Output Leakage Current
GND < VI < VCC GND < VI < VCC, Output Disabled 100 MHz 83 MHz 66 MHz 40 MHz
1 -1
VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC
ISB1 ISB2
Automatic CE Power-down Current-- TTL Inputs Automatic CE Power-down Current-- CMOS Inputs
Max VCC, CE > VIH, VIN >VIH or VIN < VIL, f = f max Max VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = 0
Note 3. VIL (min) = -2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.
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CY7C107D CY7C1007D
Capacitance [4]
Parameter CIN: Addresses CIN: Controls COUT Output Capacitance Description Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max 7 10 10 Unit pF pF pF
Thermal Resistance [4]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board 300-Mil Wide SOJ 59.16 40.84 400-Mil Wide SOJ 58.76 40.54 Unit C/W C/W
AC Test Loads and Waveforms [5]
Z = 50 OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V 3.0V ALL INPUT PULSES 90% 10% 90% 10%
30 pF*
GND
Rise Time: 3 ns
(a)
High-Z characteristics: 5V OUTPUT INCLUDING JIG AND SCOPE 5 pF
(b)
Fall Time: 3 ns
R1 480
R2 255
(c)
Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c).
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CY7C107D CY7C1007D
Switching Characteristics (Over the Operating Range) [6]
Parameter Read Cycle tpower [7] tRC tAA tOHA tACE tLZCE tHZCE tPU tPD
[10] [10] [11]
Description Min VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid CE LOW to Low Z
[8]
7C107D-10 7C1007D-10 Max
Unit
100 10 10 3 10 3 5 0 10 10 7 7 0 0 7 6 0 3 6
s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE HIGH to High Z [8, 9] CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[8] [8, 9]
Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. 9. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (c) of "AC Test Loads and Waveforms [5]" on page 4. Transition is measured when the outputs enter a high impedance state. 10. This parameter is guaranteed by design and is not tested. 11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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CY7C107D CY7C1007D
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR [5] tR
[12]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Conditions VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V
Min 2.0
Max 3
Unit V mA ns ns
0 tRC
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V tCDR
VDR > 2V
4.5V tR
CE
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [13, 14]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 [14, 15]
ADDRESS tRC CE tACE tLZCE DATA OUT HIGH IMPEDANCE DATA VALID tPD 50% 50% ICC ISB tHZCE HIGH IMPEDANCE
VCC SUPPLY CURRENT
tPU
Notes 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. 13. Device is continuously selected, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW.
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CY7C107D CY7C1007D
Switching Waveforms(continued)
Write Cycle No. 1 (CE Controlled) [16]
tWC ADDRESS tSA CE tAW tPWE WE tSD DATA IN DATA VALID HIGH IMPEDANCE tHD tHA tSCE
DATA OUT
Write Cycle No. 2 (WE Controlled) [16]
tWC ADDRESS tSCE CE tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED tLZWE HIGH IMPEDANCE tHD tAW tPWE tHA
Truth Table
CE H L L WE X H L High Z Data Out High Z DOUT Read Write Mode Power-Down Standby (ISB) Active (ICC) Active (ICC) Power
Note 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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CY7C107D CY7C1007D
Ordering Information
Speed (ns) 10 Ordering Code CY7C107D-10VXI CY7C1007D-10VXI Ordering Code Definitions CY 7 C 1 xx7 D - 10 VX I Temperature Range: I = Industrial Package Type: VX = 28-pin Molded SOJ (Pb-free) Speed: 10 ns D = C9, 90 nm Technology xx7 = 07 or 007 = (400-Mil / 300-Mil) 1-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Package Diagram 51-85032 51-85031 Package Type 28-pin (400-Mil) Molded SOJ (Pb-free) 28-pin (300-Mil) Molded SOJ (Pb-free) Operating Range Industrial
Please contact your local Cypress sales representative for availability of these parts.
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CY7C107D CY7C1007D
Package Diagrams
Figure 1. 28-pin (400-Mil) Molded SOJ, 51-85032
51-85032 *D
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CY7C107D CY7C1007D
Package Diagrams(continued)
Figure 2. 28-pin (300-Mil) Molded SOJ, 51-85031
51-85031 *D
All product and company names mentioned in this document may be the trademarks of their respective holders.
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CY7C107D CY7C1007D
Document History Page
Document Title: CY7C107D/CY7C1007D, 1-Mbit (1M x 1) Static RAM Document Number: 38-05469 REV. ** *A *B ECN NO. 201560 233722 263769 Issue Date See ECN See ECN See ECN Orig. of Change SWI RKF RKF Description of Change Advance Information data sheet for C9 IPP DC parameters modified as per EROS (Spec # 01-02165) Pb-free offering in Ordering Information Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics Table Shaded Ordering Information Reduced Speed bins to -10 and -12 ns Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information Table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3 Changed ICC specs from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz Updated Package Diagrams Added Ordering Code Definitions.
*C *D
307601 560995
See ECN See ECN
RKF VKN
*E *F *G
802877 2898399 3104943
See ECN 03/24/2010 12/08/2010
VKN AJU AJU
Document #: 38-05469 Rev. *G
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(c) Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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